The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations.
As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate of the planar cell. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
As a result of the problems associated with the use of planar capacitors for high-density DRAM memories, manufacturers are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
U.S. Pat. No. 5,130,885, hereby incorporated by reference, discloses the use of a silicon-germanium alloy having a rough surface morphology as the capacitive surface of the storage-node plate of the cell capacitor along with the use of a cell dielectric layer which exhibits the property of bulk-limited conduction. In bulk limited materials, the dielectric film's properties dominate the amount of leakage current through a capacitor. For such a capacitor, the material used for the top and bottom electrodes plays an insignificant part in determining the leakage current through a capacitor. That is to say, a capacitor having both plates made of, say aluminum, would possess very nearly the same conduction properties as would a capacitor with conductively doped polysilicon or silicon-germanium electrodes. Studies have shown that a dielectric material, such as silicon nitride, exhibits bulk-limited conduction when the silicon nitride film thickness is greater than 100 .ANG..
However, advances in equipment technology, used to deposit films, has provided the ability to deposit thin dielectric films, such as tantalum pentoxide (Ta.sub.2 O.sub.5) and silicon nitride (Si.sub.3 N.sub.4) that exhibit electrode-limited conduction. Using the advances in equipment to deposit thin dielectrics provide consistent film thickness which exhibit excellent reliability in terms of consistent dielectric properties throughout the film. Taking advantage of these films for use in DRAM fabrication presents new challenges over known processing techniques. The present invention teaches how to take advantage of the electrode-limited conduction in these dielectric films and thus provides methods for forming a highly reliable storage capacitor, as will become apparent in the following disclosure.